The $265 billion that won’t keep you shipping

Fabrication-capacity announcements are outpacing real reductions in geopolitical risk, and chip sovereignty is nowhere near solved. New fabs will expand capacity, but companies will remain exposed unless they understand and address the dependencies beneath their direct vendors.

New fabrication capacity addresses only one layer of risk

Headlines suggest the chip problem is being solved by a wave of new fabrication plants. TSMC has announced a planned $265 billion Arizona investment covering 10 fabs, two advanced-packaging facilities, and an R&D center. Samsung expects to invest more than $37 billion across its Central Texas semiconductor ecosystem, Intel is building two Ohio fabs, and Micron’s planned New York memory complex could reach $100 billion over multiple decades [1].

Much of that capacity, however, is still years away. TSMC’s first Arizona fab entered high-volume production in the fourth quarter of 2024, and its second is expected to begin volume production in 2027. Samsung expects its Taylor facility to become operational by the end of 2026. Intel plans to begin operating its first Ohio module in 2030 to 2031 and its second in 2032, while Micron expects New York production to begin in 2030 and ramp up throughout the decade [1].

Timing is only part of the issue, however. Even once these facilities are operating, they will produce wafers, the thin silicon discs from which chips are cut, rather than finished hardware. Chips still need advanced packaging, substrates, assembly, testing, memory, and logistics before they can ship in a finished product. Those downstream steps may remain constrained for 3 to 5 years as new front-end facilities open [2]. Building wafer capacity and securing finished-product supply are not the same thing, and that gap is where much of the risk remains.

Two vendors can still share one point of failure

Enterprise hardware buyers often assume they are diversified, because they purchase from two chip vendors. However, those vendors may still depend on the same foundry, packaging provider, substrate material, or equipment supplier. A disruption at a point of shared dependency can therefore affect both vendors at the same time.

That overlap is common across the semiconductor supply chain. Ajinomoto supplies nearly all of the Ajinomoto Build-up Film, or ABF, used in advanced package substrates. ASML is the only commercial supplier of extreme-ultraviolet, or EUV, lithography systems used to manufacture the most advanced chips. Nvidia and AMD compete directly, yet both rely on substrates from the same small group of Japanese suppliers [3].

For diversification to reduce risk, it has to extend beyond direct vendors. Two suppliers that rely on the same upstream input still leave the buyer exposed to a single point of failure. The companies managing this risk most effectively map dependencies through tier-2 and tier-3 suppliers and assess vendors not only on price and direct capacity, but also on how well each has secured its own supply chain [3].

Critical chokepoints remain highly concentrated

Several critical inputs and production steps are still concentrated among a small number of suppliers and geographies. TSMC holds an estimated 90% or more of Chip-on-Wafer-on-Substrate, or CoWoS, advanced-packaging capacity. Roughly 90% of the world’s most advanced sub-7-nanometer logic is fabricated in Taiwan, while China accounted for approximately 99% of global primary gallium production in 2024 [2][7].

That concentration means securing wafer capacity alone does not remove the risk. AMD saw this directly in 2021 and 2022, when it had silicon available but could not ship finished parts because substrate supply was constrained [4].

The right response depends on whether a viable alternative exists. Where it does, companies should qualify at least two sources for critical components, assembly steps, and logistics lanes. Where alternatives are limited, as with EUV equipment and ABF, companies need mitigation plans tailored to the exposure, including strategic inventory, long-term capacity agreements, and written disruption scenarios. In either case, the risk map should extend beyond wafer fabrication to include packaging, test, substrates, memory, and logistics.

What resilience actually looks like

Two design choices matter most. First, products should be designed so that critical components can be replaced without forcing a full redesign. Open, modular standards can reduce the chance that the loss of one part brings production to a stop [6].

The same principle applies to suppliers. A second source listed on a bill of materials is not necessarily ready to take over. Backup suppliers need to be qualified before a disruption occurs, a process that can take about 6 months for commodity components and 3 to 5 years for automotive-grade parts [5].

That lead time makes early preparation essential. Companies that wait until a primary supplier is disrupted move to the back of the queue, where lead times can reach 15 months or more [5]. Those that keep backup suppliers active through low-volume production and secure capacity through long-term agreements or prepayments can respond much faster when conditions change [5].

New fabrication capacity will only improve resilience if companies address these risks alongside it. That requires a detailed risk map, products designed for substitution, and qualified backup suppliers in place before a disruption occurs. Enterprise hardware companies that manage the supply chain as an operating risk, rather than only a cost line, will be better positioned to keep shipping through the next shock.

Sources and Methodology

This analysis is based on a review of public company filings and announcements, earnings-call transcripts, analyst research, expert interviews, government publications, and semiconductor trade publications published between 2024 and July 2026. Key sources include TSMC, Samsung Electronics, Intel, Micron Technology, the U.S. Department of Commerce, Future Markets, Inc., JPMorgan Research, Jefferies Research, Evercore ISI Research, China Renaissance, KGI Securities, Allianz SE, DBS Bank, and other company disclosures.

Representative data points cited in this article include fabrication-investment and production timelines, foundry and advanced-packaging concentration, ABF-substrate and gallium supply, component qualification timelines, and back-end capacity constraints. These findings were supplemented by publicly available industry commentary and research.

Selected Sources

[1] TSMC, Samsung Electronics, Intel, and Micron Technology, public announcements and disclosures regarding U.S. fabrication investments and production timelines, 2024–2026.

[2] China Renaissance, Market Research Future, and U.S. Department of Commerce publications, advanced-packaging capacity and geographic-concentration analysis, 2025–2026.

[3] Future Markets, Inc., KGI Securities, Ajinomoto Group disclosures, and Oracle carbon-disclosure reports, multi-tier dependency and substrate-concentration analysis, January–May 2026.

[4] Jefferies Research, QYResearch Group, and expert interviews, substrate and non-fab bottleneck analysis, April–June 2026.

[5] JPMorgan Research and Bernstein Research, supplier-qualification timelines, long-term agreements, and back-end capacity, January–June 2026.

[6] Company filings from Wiwynn, ECS, and Leonardo DRS; Oppenheimer & Co.; and TD Cowen, modular design and component substitutability, 2025–2026.

[7] U.S. Geological Survey, Evercore ISI Research, Allianz SE, and Little Square Capital, critical-mineral and geopolitical-risk analysis, 2024–2026.

The views expressed are those of the authors and are intended for informational purposes only. Readers should independently evaluate underlying assumptions and source materials before making investment or transaction decisions.